Two-dimensional analytical models for asymmetric fully depleted double-gate strained silicon MOSFETs  

Two-dimensional analytical models for asymmetric fully depleted double-gate strained silicon MOSFETs

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作  者:刘红侠 李劲 李斌 曹磊 袁博 

机构地区:[1]Key Laboratory of Ministry of Education for Wide Bandgap Semiconductor Devices,School of Microelectronics,Xidian University

出  处:《Chinese Physics B》2011年第1期566-572,共7页中国物理B(英文版)

基  金:Project supported by the National Natural Science Foundation of China(Grant Nos.60976068and60936005);the Cultivation Fund of the Major Science and Technology Innovation,Ministry of Education,China(Grant No.708083);Specialized Research Fund for the Doctoral Program of Higher Education(Grant No.200807010010);the Fundamental Research Funds for the Central Universities

摘  要:This paper develops the simple and accurate two-dimensional analytical models for new asymmetric double-gate fully depleted strained-Si MOSFET. The models mainly include the analytical equations of the surface potential, surface electric field and threshold voltage, which are derived by solving two dimensional Poisson equation in strained-Si layer. The models are verified by numerical simulation. Besides offering the physical insight into device physics in the model, the new structure also provides the basic designing guidance for further immunity of short channel effect and draininduced barrier-lowering of CMOS-based devices in nanometre scale.This paper develops the simple and accurate two-dimensional analytical models for new asymmetric double-gate fully depleted strained-Si MOSFET. The models mainly include the analytical equations of the surface potential, surface electric field and threshold voltage, which are derived by solving two dimensional Poisson equation in strained-Si layer. The models are verified by numerical simulation. Besides offering the physical insight into device physics in the model, the new structure also provides the basic designing guidance for further immunity of short channel effect and draininduced barrier-lowering of CMOS-based devices in nanometre scale.

关 键 词:STRAINED-SI double-gate MOSFET surface potential short-channel effect 

分 类 号:TN386.1[电子电信—物理电子学] TP391.9[自动化与计算机技术—计算机应用技术]

 

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