片上网络核心芯片的验证与测试  

Verification and testing of core chip of network-on-chip

作　　者：吕耀刚[1] 蒋林[2] 刘钊远[1] 支亚军[1] 

机构地区：[1]西安邮电学院计算机学院,陕西西安710061 [2]西安邮电学院电子工程学院,陕西西安710061

出　　处：《电子设计工程》2011年第1期66-69,共4页Electronic Design Engineering

基　　金：国家高技术研究发展计划(863计划)资助项目(2007AA01Z111)

摘　　要：为提高芯片验证与测试的可靠性,针对片上网络核心芯片的结构特点,设计出一种基于宿主机/目标机通信模式的测试系统。重点描述了测试系统软硬件的设计与实现,并采用Stratix系列FPGA芯片进行原型测试和验证。实验结果表明,该系统可对芯片的复位、实现功能及稳定性进行全面测试,而且原理简单、操作方便、运行稳定,极大地提高了芯片测试的可靠性和速度。In order to enhance the reliability of chip＇s verification and testing, the article designs a test system of communication model based on host and target machine, for the structural characteristics of the network-on-chip. It focuses on designing and implementation of system＇s hardware and software, and uses FPGA chip of Stratix series to test and verify. The experiment results show that this system has simple principle, convenient operation, and stable operation. It can achieve a comprehensive test of chip＇s reset, functions and stability, which improves the reliability and speed of chip testing.

关 键 词：片上网络 验证 测试系统 ARM 

分 类 号：TP393[自动化与计算机技术—计算机应用技术] TN407[自动化与计算机技术—计算机科学与技术]