电路系统中的闩锁效应及其预防设计  

Latch-up Effect and Its Prevention in Circuit Systems Based on CMOS

作　　者：吴允平[1] 苏伟达[1] 李汪彪[1] 蔡声镇[2] 

机构地区：[1]福建师范大学电子信息工程系,福建福州350007 [2]福建师范大学软件学院,福建福州350007

出　　处：《现代电子技术》2011年第1期170-172,共3页Modern Electronics Technique

基　　金：福建省自然科学基金项目(2010J01326);福建省科技厅项目(2008H0022;2009H0018);校教师项目(2008100214)

摘　　要：针对CMOS集成电路的闩锁效应,围绕实际应用的电路系统中易发生闩锁效应的几个方面进行了详细说明,提出了采用严格的上电时序、基于光耦的电路隔离设计和热插拔模块的接口方法,可以有效地降低发生闩锁效应的概率,从而提高电路系统的可靠性。The latch-up effect which is easy to appear in CMOS IC and the widely used circuit systems with an attributive defect leading to failure of circuits is elaborated. Key factors causing latch-up effect are discussed. Furthermore, the special interface method of critical power-on time-sequence, circuit isolatation design based on photo-electric coupler and hot-plugging modules is proposed. It testified in applications that the designs are helpful to reduce the risk of latch-up effect.

关 键 词：闩锁效应 上电时序 光耦 热插拔 

分 类 号：TN702-34[电子电信—电路与系统]