基于ARMv4T架构指令集的乘法器设计  

Design of multiplier based on instruction set of ARMv4T architecture

作　　者：陈海民[1] 李峥[1] 杨先文[1] 

机构地区：[1]解放军信息工程大学电子技术学院,郑州450004

出　　处：《计算机应用研究》2011年第2期587-590,共4页Application Research of Computers

基　　金：国家自然科学基金资助项目(61072047);现代通信国家重点实验室基金资助项目(9140C1106021006);郑州市创新型科技人才队伍建设工程(096SYJH21099)

摘　　要：针对硬件IP核的速度和面积两大性能指标,提出了基于可变执行周期的多周期乘法器设计思想,设计出一款适用于32位嵌入式微处理器的乘法器模块。该乘法器兼容ARMv4T架构的所有乘法指令,同时引入字节判断机制,可以根据操作数的特点在2～5个周期内执行完毕。采用Radix-4 Booth编码,只需两级压缩树进行部分积压缩。乘加运算的基址寄存器数据作为部分积进入压缩树,节约了一个单独的执行周期。实验结果表明,该设计占用芯片资源少,且结构简单高效。Aiming at the two performance targets of speed and area for hardware IP core,this paper proposed the design of multiplier suitable for 32-bit microprocessor,with the idea of multi-cycle multiplier based on adjustable execution cycle.It was compatible with all multiplicative instructions of ARMv4T architecture,simultaneously introduced byte-judgment mechanism which could achieve the instruction in 2~5 cycles according to the operand＇s characteristic.The design adopted Radix-4 Booth encoding,needing only two-level 4-2 compress octree.The base register data of multiply-accumulate came into compressors as a partial product,saving a single execution cycle.The experiment result shows that it owns small chip area,with easy and high-performance configuration.

关 键 词：ARMv4T架构 乘法器 可变执行周期 Radix-4Booth编码 4-2压缩树 

分 类 号：TP342.22[自动化与计算机技术—计算机系统结构]