一种基于FPGA的高斯随机数生成器的设计与实现  

Design and Implementation of a FPGA Based Gaussian Random Number Generator

作　　者：谷晓忱[1] 张民选[1] 

机构地区：[1]国防科学技术大学计算机学院PDL重点实验室,长沙410073

出　　处：《计算机学报》2011年第1期165-173,共9页Chinese Journal of Computers

基　　金：国家"八六三"高技术研究发展计划项目基金(2009AA01Z124;2009AA01Z104;2009AA01Z102)资助

摘　　要：基于FPGA的高斯随机数生成器需要满足可重构、高吞吐率和高硬件资源使用效率等要求.文中提出了一种易于硬件实现的状态转换逻辑结构,并给出了均匀分布随机数周期和输出位宽的配置方法和配置原则.文中详细分析了应用"最值分析法"和"静态误差分析法"求解Box Muller算法实现过程中各操作数位宽的具体过程.硬件实现结果在Xilinx Vertex 5上的工作速度为491 MHz,吞吐率为9.82×108samples/second,硬件资源使用效率为2.085×106samples/second/slice.文中作者使用DIEHARD测试集、χ2和K-S方法对产生的随机数质量进行了检测,文中给出了结果.A good FPGA based Gaussian Random Number Generator has to be reconfigurable for different applications, while running fast and acquiring a high throughput per slice. In this paper, a hardware structure of the Transform Module is proposed. The configuration process and princi ple of the period and output bit width of uniform random numbers are introduced. For the gener- ation of Gaussian random numbers, methods for bit-width optimization of the fixed point operands are introduced in details. Implementation results on Xilinx Vertex 5 FPGA show that the proposed hardware design could acquire a frequency as high as 491 MHz, while the corresponding throughput is 9.82×10Ssamples/second and the throughput per slice is 2. 085 × 106 samples/second/slice. DIEHARD test suit, X2 and K-S method are used to test the quality of the generated random numbers here.

关 键 词：现场可编程门阵列 硬件加速器 高斯随机数产生 均匀分布随机数产生 可重构计算 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]