一种基于PWM的CMOS误差放大器的设计  

Design of a CMOS error amplifier based on PWM

作　　者：张承[1] 唐宁[1] 邓玉清[1] 

机构地区：[1]桂林电子科技大学通信与信息学院,广西桂林541004

出　　处：《电子设计工程》2011年第3期38-41,共4页Electronic Design Engineering

摘　　要：为解决PWM控制器中输出电压与基准电压的误差放大问题,设计了一款高增益、宽带宽、静态电流小的新型误差放大器,通过在二级放大器中间增加一级缓冲电路,克服补偿电容的前馈效应,同时消除补偿电容引入的零点。在Cadence软件平台上,经过交流和瞬态仿真,电路0 dB带宽达到55.5 MHz,电压开环增益约67.2 dB,相位裕度为83.0°上升建立时间和下降建立时间分别为6.7 V/μs和5.7 V/μs共模抑制比为49.17 dB,电源抑制比为71.39 dB。该误差放大器已经应用到了PWM芯片中,使得PWM最大、最小占空比可调,大幅提升了芯片系统的整体性能。In order to solve the error amplify between output voltage and reference voltage in PWM controller. This paper presents a new type of error amplifier, which has a good performance of high gain, high bandwidth and low quiescent current. By increasing a buffer circuit in the middle of the secondary amplifier,the error amplifier could overcome the feed-forward effect of compensation capacitor while eliminating the zero spot lead by the compensation capacitor. In the Cadence software platform, through AC and transient simulation, the test result indicates that the circuit 0dB bandwidth is 55.SMHz, open-loop voltage gain is 67.2dB, phase margin is 83.0° ,and rise and fall time of the establishment separately are 6.7V/μs and 5.7V/μs,CMRR is 49.17dB, PSRR is71.39dB, The maximum and minimum duty circle of the output of the PWM circuit could be controlled with the help of this type of error amplifier, which increases the performance of the whole system.

关 键 词：PWM 误差放大器 高增益 宽带宽 占空比 

分 类 号：TN492[电子电信—微电子学与固体电子学]