外延CeO_2高k栅介质层的结构及介电性能  

Structure and dielectric properties of epitaxial CeO_2 thin films for high-k gate dielectric layer

作　　者：娄建忠[1] 代鹏超[1,2] 李曼[2] 赵冬月[2] 刘保亭[2] 

机构地区：[1]河北大学电子信息工程学院,河北保定071002 [2]河北大学物理科学与技术学院,河北保定071002

出　　处：《电子元件与材料》2011年第3期32-35,共4页Electronic Components And Materials

基　　金：国家自然科学基金资助项目(No.11074063);河北省教育厅科学研究计划资助项目(No.2007416);河北省科学技术厅科学技术研究与发展指导计划资助项目(No.07215154);河北大学博士基金资助项目(No.y2006091;y2007091);河北省应用基础研究计划重点基础研究资助项目(No.10963525D)

摘　　要：利用脉冲激光沉积两步生长法在Si(111)衬底上制备了厚度为10～40 nm的外延CeO2薄膜,构建了Pt/CeO2/Si MOS结构,研究了CeO2薄膜的界面及介电性能。实验发现,界面处存在的电荷对MOS结构C-V特性的测量有较大影响,采用两步生长法制备的外延CeO2薄膜在保持较大介电常数的同时有效降低了界面态密度。由等效氧化物厚度-物理厚度曲线得出CeO2薄膜的介电常数为37;根据Hill-Coleman法计算出CeO2薄膜界面态密度为1012量级。Epitaxial CeO2 thin films, 10-40 nm thick, were deposited on Si（lll） substrate by the pulsed laser deposition two-step method. The metal-oxide-semiconductor（MOS） structures were further fabricated to evaluate the interface and dielectric properties of CeO2 films. The results show that the C-V characteristics can be greatly affected by the interface charges. The epitaxial CeO2 thin films, which are deposited by two-step process, possess larger permittivities and lower interface state density. The permittivity calculated from the EOT-/phys characteristics curve is 37, and according to Hill-Coleman method, the interface state density is 10^12 order of magnitude.

关 键 词：硅衬底外延CeO2薄膜 高k栅介质层 介电性能 

分 类 号：TN384[电子电信—物理电子学]