检索规则说明:AND代表“并且”;OR代表“或者”;NOT代表“不包含”;(注意必须大写,运算符两边需空一格)
检 索 范 例 :范例一: (K=图书馆学 OR K=情报学) AND A=范并思 范例二:J=计算机应用与软件 AND (U=C++ OR U=Basic) NOT M=Visual
作 者:施长治[1,2] 崔虹云[1,3] 刘晓为[1,2] 揣荣岩[4] 李智[1]
机构地区:[1]哈尔滨工业大学航天学院,哈尔滨150001 [2]哈尔滨工业大学微系统与微结构制造教育部重点实验室,哈尔滨150001 [3]佳木斯大学理学院,佳木斯154007 [4]沈阳工业大学信息科学与工程学院,沈阳110178
出 处:《纳米技术与精密工程》2011年第1期11-15,共5页Nanotechnology and Precision Engineering
基 金:国家自然科学基金资助项目(60776049);辽宁省科学技术基金资助项目(20072036);辽宁省教育厅创新团队资助项目(2007T130)
摘 要:为了提高基于多晶硅纳米薄膜的压阻传感器的性能及成品率,对不同厚度多晶硅薄膜的电阻电学修正特性进行了研究.采用低压化学气相淀积(LPCVD)工艺,620℃下制备多晶硅薄膜.通过固相扩散法实现高掺硼,并基于光刻工艺制作成电阻.实验结果表明,在薄膜电阻上施加高于阈值的电流,可有效降低电阻值.薄膜厚度的变化改变了薄膜结晶度及晶粒尺寸,从而影响其修正阈值电流密度及修正速率.用所建立的晶界填隙原子-空位对模型对电学修正现象进行了理论分析,认为该现象是大电流激励产生的焦耳热导致晶界发生逐层重结晶,从而增大载流子迁移率的结果.研究表明,该方法可用于高掺杂多晶硅电阻的封装后调阻.In order to improve the performance and yield of piezoresistive sensors based on polysilicon nanofilms,the electrical trimming properties of polysilicon thin films with different thicknesses were investigated in this paper.The thin films were prepared at 620 ℃ by low pressure chemical vapour deposition(LPCVD).Then the films were heavily doped with boron with solid diffusion and fabricated into resistors by photolithography.The experimental results indicate that when applied the current higher than a threshold,the resistance of thin film resistor can be reduced effectively.Moreover,the change in film thickness alters the film crystallinity and grain size,so that the threshold trimming current density and trimming rate are affected.The electrical trimming was analyzed theoretically based on the established interstitial-vacancy pair model of grain boundary,which attributes it to the layer-by-layer recrystallization of grain boundary resulting from Joule heat generated by large current and the increase of the carrier mobility.Finally,it is concluded that this method can be used for the post-packaging trimming of highly doped polysilicon resistors.
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在链接到云南高校图书馆文献保障联盟下载...
云南高校图书馆联盟文献共享服务平台 版权所有©
您的IP:3.149.249.140