异步FIFO在FPGA与DSP通信中的运用  

Application of Asynchronous FIFO in Communication Between FPGA and DSP

作　　者：胡波[1] 李鹏[1] 

机构地区：[1]西安电子科技大学电子工程学院,陕西西安710071

出　　处：《电子科技》2011年第3期53-55,61,共4页Electronic Science and Technology

摘　　要：利用异步FIFO实现FPGA与DSP进行数据通信的方案。FPGA在写时钟的控制下将数据写入FIFO,再与DSP进行握手后,DSP通过EMIFA接口将数据读入。文中给出了异步FIFO的实现代码和FPGA与DSP的硬件连接电路。经验证,利用异步FIFO的方法,在FPGA与DSP通信中的应用,具有传输速度快、稳定可靠、实现方便的优点。This article introduces the method of using asynchronous FIFO in communication between FPGA and DSP.The FPGA writes the data into FIFO under the control of the writing clock.After hand shaking with the FPGA,the DSP reads the data through the EMIFA interface.The article gives the detailed codes for asynchronous FIFO and the electric circuits for DSP.It is shown that the application of the asynchronous FIFO method in the communication between FPGA and DSP has the advantages of high transmission speed,stability,reliability and easy realization.

关 键 词：异步FIFO FPGA与DSP数据通信 EMIFA 

分 类 号：TN919.5[电子电信—通信与信息系统]