一种高能效的面向单发射按序处理器的预执行机制  

An Energy-Efficient Executing Ahead Mechanism for Improving the Performance of Single-Issue In-Order Microprocessors

作　　者：王箫音[1] 佟冬[1] 党向磊[1] 冯毅[1] 程旭[1] 

机构地区：[1]北京大学微处理器研究开发中心,北京100871

出　　处：《电子学报》2011年第2期458-463,共6页Acta Electronica Sinica

基　　金：国家863高技术研究发展计划(No.2006AA010202)

摘　　要：按序处理器凭借其在低成本、低功耗和高可扩展能力等方面的优势,越来越多地应用于多核处理器中.为进一步满足单线程程序的性能需求,有效提升按序处理器的访存性能至关重要.本文面向典型的单发射按序处理器提出一种高能效的预执行机制,充分利用预执行过程中的有效访存结果与计算结果加速程序的执行.为达到高能效的目标,一方面,本文提出基于收益预测的预执行动态调整策略,该策略采用三种收益预测方法来识别并避免无收益的预执行阶段.另一方面,本文采用基于信心估计的转移预测机制对预执行期间无法及时判定的转移指令进行优化.实验结果表明,在平均情况下,本文方法将基础处理器的性能提升24.14%,而能耗仅增加4.31%.与已有的两种预执行方法相比,本文方法在获取可比的性能优化效果的同时,能耗开销分别降低7.72%和10.72%,从而使能效性分别提高10.3%和11.39%.In-order microprocessors are increasingly adopted in a variety of multi-core chips due to their advantages in low power,low cost and high scalability.To further satisfy the performance requirement of single-thread applications,improving the load latency tolerance of in-order microprocessors is crucial.We propose an energy-efficient executing ahead mechanism which pre-executes the following instructions instead of stalling the processor when a long-latency cache miss occurs.This mechanism dynamically adjusts the executing ahead policy based on the prediction results of the performance benefit predictor to identify and eliminate the useless executing ahead periods.A confidence-based branch predictor is proposed for unresolvable branches during the useful executing ahead periods.Experimental results demonstrate that the performance is increased by 24.14% only with 4.31% energy overhead on average.Compared with two existing methods,the mechanism proposed in this paper decreases the energy consumption by 7.72% and 10.72% while achieving comparable performance enhancement,thus improves the energy-efficiency by 10.3% and 11.39%,respectively.

关 键 词：单发射按序处理器 预执行 访存延时包容 

分 类 号：TP302.7[自动化与计算机技术—计算机系统结构]