SDH中HDB3编解码电路的FPGA实现  

Implement of HDB3 codec circuits by FPGA in SDH system

作　　者：崔洲涓[1] 胡辽林[1] 

机构地区：[1]西安理工大学机械与精密仪器工程学院,西安710048

出　　处：《光通信技术》2011年第3期40-42,共3页Optical Communication Technology

基　　金：陕西省教育厅科学研究计划(2010JK716)资助

摘　　要：SDH传输系统中,为了使传输波形便于提取定时信息和检错,选择HDB3码。通过Verilog HDL编写程序代码,在Quartus Ⅱ 9.0环境下,完成了布局布线和时序仿真,给出了仿真结果,选用ALTERA公司的CycloneⅢ系列FPGA芯片,实验结果与理论输出值一致。In the SDH transmission system ,in order to make the waveform meet the requirements of extracting the timing information conveniently and capability of error detection, it chooses the common channel transmission code which is third-order high-density bipolar code （HDB3）.This paper aims to introduce the coding and decoding principle of HDB3. The selected FPGA device （ALTERA Corp Cyclone Ⅲ series） is written by Verilog HDL code in the Quartus Ⅱ9.0 environment to accomplish routing and timing simulation. The simulation results and experimental results are consistent with the theoretical output. As the features high integration, low power consumption and repeated programmable of FPGA.

关 键 词：HDB3码 FPGA SDH VERILOG HDL 

分 类 号：TN911[电子电信—通信与信息系统]