一种三维SoCs绑定前的测试时间优化方法  

Optimizing method for pre-bond test time on three-dimensional SoCs

作　　者：欧阳一鸣[1] 刘蓓[1] 梁华国[1] 

机构地区：[1]合肥工业大学计算机与信息学院,合肥230009

出　　处：《电子测量与仪器学报》2011年第2期164-169,共6页Journal of Electronic Measurement and Instrumentation

基　　金：国家自然科学基金(编号:60876028)资助项目;国家自然科学基金重点项目(编号:60633060)资助项目;安徽省自然科学基金(编号:090412034)资助项目;安徽高校省级自然科学研究重点项目(编号:KJ2010A269)资助项目

摘　　要：提出了一种在引脚和功耗限制下3D SoCs的绑定前测试方法。对IP核细粒度划分,将每个IP核的触发器数均衡分布到各层芯片上,利用TSV进行互连,设计出一种新颖的三维结构的测试外壳扫描链,同时在功耗和引脚限制下对IP核进行测试调度。实验结果表明,该方法使得芯片的测试时间获得大幅度降低的同时对功耗的需求很小。A test method for 3D SoCs under pre-bond test pins and power consumption constraint is presented in this paper. Use fine-granularity partitioning for cores, the number of flip flops in each IP core are partitioned balanced into each layers and interconnected by TSV. A novel 3D IC core wrapper scan-chain is designed and a SoC test scheduling method is proposed under pre-bond test pins and power consumption. Experimental results demonstrate that the test time can be reduced sharply and need less power consumption on 3D SoCs compared to the traditional 2D SoCs.

关 键 词：三维片上系统 三维扫描链设计 测试调度 测试时间 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]