一种动态可重构Reed-Solomon译码器的设计  

Design of a Dynamically Reconfigurable Architecture for Reed-Solomon Decoder

作　　者：谭思炜[1] 潘红兵[1] 

机构地区：[1]海军工程大学电子工程学院,湖北武汉430033

出　　处：《计算机测量与控制》2011年第3期673-675,678,共4页Computer Measurement &Control

摘　　要：针对RS译码器结构复杂,资源消耗大的问题,提出了一种基于动态可重构技术的RS译码器;该译码器将伴随多项式计算和钱氏搜索算法在同一个可重构模块RSCM中通过动态改变电路结构,以时分复用的方式实现;给出了基于状态机的译码控制器,实现各功能模块的调用;采用VHDL语言实现,在Quartus Ⅱ 7.2环境下进行仿真;结果表明,该译码器能有效降低硬件资源占用率,最高时钟频率达到124MHz。In order to solve the problem of complex architecture and large resource consuming in RS decoder, a dynamically reconfigu table RS decoder is presented. In the decoder, the syndrome calculation and Chien＇ s search algorithm can be realized in the reconfigurahle syndrome and Chien＇ s module （RSCM） by reconfiguring the circuit architecture dynamically at discrete time. A decode control module based on state machine is given and is in charge of controlling the function modules in RS decoder. The design is realized by VHDL language in Quartus II 7.2. As it is shown in the result, the encoder could reduce the consuming in hardware resource, and the maximum frequency of this chip could reach at 124MHz.

关 键 词：动态可重构 RS译码器 FPGA 伴随多项式 钱氏搜索 

分 类 号：TP331[自动化与计算机技术—计算机系统结构]