基于CBPSO的板级电路测试性设计优化方法研究  

Optimizing method of board level circuit design for testability based on chaos particle swarm optimization

作　　者：吕晓明[1] 刘晓芹[1] 黄考利 刘耀周 

机构地区：[1]军械工程学院,河北石家庄050003 [2]军械技术研究所,河北石家庄050003

出　　处：《系统工程学报》2010年第6期791-797,共7页Journal of Systems Engineering

摘　　要：基于边界扫描的板级电路在测试性改善一定条件下,设计复杂性最小化问题属于组合优化问题,同时也是NP-难题.针对该组合优化问题提出了基于混沌二进制粒子群优化的求解方法.该方法在二进制粒子群优化的基础上,对当前最佳粒子以变概率进行混沌优化,引导粒子跳出局部最优继续在全局范围内搜索,从而克服二进制粒子群的"早熟"收敛.通过实例验证,该算法在优化效果、搜索效率等方面均获得了较好的结果.事实证明,该算法能有效地应用于板级电路的测试性设计优化.Under a certain condition of testability improvement of board-level circuit based on boundary scan,minimizing the design complexity belongs to combination optimizing problem,and is also a NP-hard problem.In order to solve this problem.This paper puts forward a method based on chaos binary particle swarm optimization（BPSO）.This method first makes the binary particle swarm optimization,and then further uses the chao optimization for the best current particle to lead the particle out of local optimum and search in the large.In this way,the drawback of prematurity convergence of BPSO can be overcome.An example was given,and better results were obtained,which demonstrated that this method can be applied to the optimization of DFT（design for testability） for board-level circuit effectively.

关 键 词：测试性设计 边界扫描 板级电路 混沌优化 二进制粒子群优化 

分 类 号：TP206[自动化与计算机技术—检测技术与自动化装置]