基于802.11a的FFT/IFFT处理器设计  

Design of a FFT/IFFT Processor for 802.11a

作　　者：吴斌[1] 姜鑫[1,2] 周玉梅[1] 

机构地区：[1]中国科学院微电子研究所,北京100029 [2]电子科技大学电子工程学院,四川成都610054

出　　处：《微电子学与计算机》2011年第4期61-64,共4页Microelectronics & Computer

基　　金：“新一代宽带无线移动通信网”国家科技重大专项(2009ZX03007-002)

摘　　要：设计了一种应用于802.11a的64点FFT/IFFT处理器.采用单蝶形4路并行结构,提出了4路并行无冲突地址产生方法,有效地提高了吞吐率,完成64点FFT/IFFT运算只需63个时钟周期.提出的RAM双乒乓结构实现了对输入和输出均为连续数据流的缓存处理.不仅能实现64点FFT和IFFT,而且位宽可以根据系统任意配置.为了提高数据运算的精度,设计采用了块浮点算法,实现了精度与资源的折中.16位位宽时,在HJTC 0.18μmCMOS工艺下综合,内核面积为:0.626 7 mm2,芯片面积为:1.35 mm×1.27 mm,最高工作频率可达300 MHz,功耗为126.17 mW.In this paper, we present a 64 point FFT/IFFT processer developed primarily for the application in a OFDM based IEEE 802. 11a WLAN baseband processor. The proposed processor uses the four-parallel architecture of single butterfly to efficiently improve throughput, and requires only 63 clock cycles for a 64 points FFT/IFFT. Double PingPang architecture is proposed to perform storage of both input and output streaming data. The proposed processor not only supports the operation of FFT/IFFT in 64 points but can also config bits-width arbitrarily accord- ing to system demand. In addition, it uses Block-floating point algorithm which can improve precision of the proces- sor , balances precision and resource. The proposed processor of 16 bits is designed in a HJTC 0. 18μm CMOS process, the core area is 0. 626 7 mm2 , the tape-out area is 1.35 min×1.27 mm. At the highest clock frequency is 300 MHz, the power is 126. 17 mW.

关 键 词：FFT IFFT 块浮点 并行无冲突地址 

分 类 号：TN92[电子电信—通信与信息系统]