基于SoPC的二维IDCT分布式算法的IP核研究  

The IP core research of 2D IDCT distributed algorithm based on SoPC

作　　者：付扬[1] 邓超[1] 

机构地区：[1]北京工商大学计算机与信息工程学院,北京100048

出　　处：《电子技术应用》2011年第4期126-129,137,共5页Application of Electronic Technique

基　　金：北京市教委面上项目资助(M200910011008)

摘　　要：研究基于SoPC的视频解码系统中二维IDCT硬件设计与实现。针对二维IDCT的运算量大、乘法运算多,导致占用FPGA资源多和系统速度慢等问题,其设计采用一维IDCT复用,研究分布式算法实现乘法累加,并使用偏移二进制编码来减小其查找表大小,其直接占用FPGA逻辑单元内的查找表LUT,没有寄存器或内置RAM。综合结果表明,芯片占用资源少、访问速度快,其最高可综合工作频率达到140.39 MHz。此外,基于Avalon总线接口实现二维IDCT IP核的SoPC Builder系统构建,在以Nios II处理器为核心SoPC视频解码系统中测试,结果表明,该IP核能提高视频解码速度20%以上,很大程度上增强了解码的实时性。Research SoPC system of two-dimensional IDCT hardware design and implementation. Two-dimensional IDCT for computing capacity, multiplication and more, making the occupation of FPGA resources and system slow and so many disadvantages, the design uses a distributed algorithm muhiply-accumulate, and use the offset binary coding to reduce the size of the lookup table can be directly FPGA logic cells using the look-up table LUT, there are no registers or internal RAM. The synthesis results show that the chip takes fewer resources, access speed, two-dimensional IDCT integrated work a maximum frequency of 140.39 MHz. Avalon bus interface based on two-dimensional IDCT IP core of the SoPC builder system construction, Testing based on SoPC video decoding system In Nios Ⅱ processor as the core, the test results show that the IP core rate increased more than 20%, largely enhanced real-time decoding.

关 键 词：可编程片上系统 IP核 离散余弦逆变换 分布式算法 偏移二进制编码 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]