一位全加器电路实现方法探讨  

Study of the Design Method of a Full Adder Circuit

作　　者：林涛[1] 

机构地区：[1]长安大学电子与控制工程学院,陕西西安710064

出　　处：《电气电子教学学报》2010年第B10期223-226,共4页Journal of Electrical and Electronic Education

摘　　要：全加器是数字系统中重要的基本单元电路，以一位全加器电路设计为例，通过对其输出函数表达式的形式变换，分别采用多种门电路及译码器、数据选择器等74系列器件进行电路设计，给出了8种电路实现形式，并简略分析了各种电路实现的优缺点。此例说明了组合逻辑电路设计的灵活性及电路实现的多样性，所采用的设计方法对其他组合逻辑电路设计具有一定的启发与指导意义。A bit full adder is a very important component in the digital system. Design of a full-adder circuit, as an example, by changing its output function expression in the form of expression, use the gates, decoder, multiplexer etc 74 series devices, the eight circuits realization form are given respectively, and briefly analyzed the advanta that the design of combinati the guiding for other design ges and disadvantages of the various circuit implementation. The examp e show onal logic circuits has mobility and variety, it could give the instructiveness and of combinational logic circuits.

关 键 词：数字系统 组合逻辑电路 全加器 设计方法 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]