多晶硅薄膜晶体管的栅电容模型  

Gate Capacitance Model of Polysilicon Thin Film Transistors

作　　者：邓婉玲[1] 

机构地区：[1]暨南大学信息科学技术学院电子工程系,广东广州510630

出　　处：《液晶与显示》2011年第2期178-182,共5页Chinese Journal of Liquid Crystals and Displays

基　　金：广东高校优秀青年创新人才培养计划(育苗工程)(No.LYM10032)

摘　　要：多晶硅薄膜晶体管具有独特的栅电容特性,即泄漏区中栅源电容的反常增大和饱和区中栅漏电容由于kink效应的增大。基于Meyer模型,考虑了泄漏产生效应和kink效应,对多晶硅薄膜晶体管的栅漏电容和栅源电容特性进行了建模研究。对实验数据进行拟合发现,提出的模型与实验数据符合得较好,能准确地预测多晶硅薄膜晶体管的栅电容特性。Polysilicon thin film transistors have unique gate capacitance features,that is,the anomalous increase of gate-to-source capacitance in leakage region and gate-to-drain capacitance in kink region.Based on the Meyer model,taking leakage generation effect and kink effect into account,gate-to-source capacitance and gate-to-drain capacitance characteristics are modeled.The good agreement between simulated model results and experimental data confirms the accuracy and efficiency of this model.

关 键 词：多晶硅薄膜晶体管 栅漏电容 栅源电容 模型 

分 类 号：TN321.5[电子电信—物理电子学]