双频双系统导航芯片的时钟树分析和设计  

Analysis and Design of Clock Tree in Dual-Frequency and Dual-System Navigation IC

作　　者：童琼[1] 张晓林[1] 苏琳琳[1] 张帅[1] 杜龙军[1] 

机构地区：[1]北京航空航天大学电子信息工程学院,北京100191

出　　处：《微电子学》2011年第2期246-250,共5页Microelectronics

摘　　要：在复杂的超大规模高速集成电路设计中,时钟树的综合与优化是芯片后端设计优化时序过程中至关重要的一环,其中时钟树的设计是最关键的部分。以SMIC 0.13μm工艺双频双系统兼容接收机数字基带导航芯片为例,根据时钟树时序要求和时钟树延迟模型,基于Synopsys的Astro工具,对芯片进行自动时钟树分析和指定时钟树结构分析,设计和优化了时钟树结构。结果表明,利用此方法得到的时钟树结构能取得更优的结果。In design of sophisticated and high-speed LSI circuit,clock tree synthesis and optimization is a key part of timing optimization in the process of back-end chip design,while clock tree design is the most crucial part.Based on timing requirements and clock tree delay model,an automatic analysis of clock tree and designation of clock tree analysis were performed.The clock tree was designed and optimized using Astro tool of Synopsys,based on SMIC＇s 0.13 μm digital baseband navigation IC for dual-frequency and dual-system compatible receiver.It has been shown that clock tree structure using the proposed method could have better results.

关 键 词：时钟树综合 时钟偏斜 时钟延时 后端设计 

分 类 号：TN402[电子电信—微电子学与固体电子学]