适用于MPEG2视频解码的VLD设计  

A VLSI Structure of Variable Length Decoder Compatible with MPEG2 Standard

作　　者：杜晓刚[1] 秦东[1] 何寅[1] 叶波[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433

出　　处：《微电子学》1999年第6期428-431,共4页Microelectronics

摘　　要：提出了一种新的适用于MPEG2 视频解码的变字长解码(VLD)结构,根据MPEG2 变字长码表的特点,通过合理的码字分割解决码字的存储问题,采用桶式移位器,使得每个时钟能处理一个码字。由于比特流中最长的码长为24 比特,故采用32 位的内部总线结构,减小了电路规模。用1.0 μm CMOS单元库进行综合,在50MHz时钟频率下工作时电路规模为6000A novel architecture for Variable Length Decoding(VLD) algorithm for MPEG2 video decoder is proposed in the paper According to the characteristics of MPEG2 DCT coefficients table,the storage of codeword is solved by proper codeword partitioning Barrel shift register is used so that each codeword can be processed in one clock period Since the longest codeword is 24 bits,32 bit data bus is used to reduce the scale of circuit The VLD is synthesized with 1 0 μm CMOS cell library,and is implemented in 4000 gates when operating at 50 MHz

关 键 词：视频解码 变字长解码 MPEG2 图像编码 

分 类 号：TN919.8[电子电信—通信与信息系统]