嵌入式虚拟协同开发环境的设计与实现  

Design and Implementation of Virtual Co-Design Environment for Embedded System

作　　者：李勃[1] 黄巾[1] 王竹平[1] 

机构地区：[1]西安微电子技术研究所,陕西西安710075

出　　处：《计算机测量与控制》2011年第4期931-934,共4页Computer Measurement &Control

摘　　要：为了提高嵌入式系统的开发效率和设计可靠性、提供在获得硬件原型之前的虚拟集成验证手段,本文引入了软硬件协同验证的概念,提出了一种新的基于网络的嵌入式虚拟协同开发环境实现方法,通过采用松耦合布局的指令集仿真器和逻辑仿真器来构建虚拟集成验证环境,并在此基础上优化逻辑仿真,分离和抑制不必要的逻辑仿真周期,有效地提高了协同验证仿真性能。For the purpose of making embedded system design quickly and safely,and providing a virtual integrated testing platform prior to obtaining a hardware prototype,the concept of software/hardware co-verification is introduced.The implementation method of a new type of net-based virtual develop environment for embedded system is described in this paper,and a virtual integrated verification environment is built by instruction set simulator and logical simulator which has a loose coupling layout.And then optimizing the logical simulation by separating and suppressing some unnecessary logical simulation cycle,to improve the simulation performance of co-verification effectively.

关 键 词：协同开发 协同验证 逻辑仿真 指令集仿真 集成开发环境 

分 类 号：TP391.9[自动化与计算机技术—计算机应用技术]