SoC芯片可测试性设计策略的实现研究  

A study on the implementation of DFT strategies for SoC design

作　　者：胡明明[1,2] 王小力[3,2] 

机构地区：[1]西安交通大学电子与信息工程学院,1723信箱陕西西安710049 [2]西安交通大学VLSI设计研究中心,陕西西安710049 [3]西安交通大学理学院,陕西西安710049

出　　处：《电路与系统学报》2011年第2期56-61,共6页Journal of Circuits and Systems

基　　金：教育部科学技术重点研究资助项目(03151)

摘　　要：本文结合实际研发要求,对基于USB2.0的数字音频编解码片上系统的可测试性设计(DFT)策略进行了研究。该系统采用UMC 0.13μm CMOS工艺,集成SPRAM、DPRAM、ROM、上电复位单元POR(Power On Reset)、降压转换器LDO(Low Drop Out regulator)、锁相环PLL(Phase Locked Loop)、电熔丝盒(e-fuse box)、ADC、USB焊盘等模块。本文采用JTAG(Joint Test Action Group)和焊盘控制逻辑PCL(Pad Control Logic)进行测试控制,使得所有模块可测试。扫描链测试采用多种优化策略,故障覆盖率达到98.06%,满足系统设计要求。存储器内建自测试(MBIST),采用并行测试和串行调试策略,将所有存储器测试时间压缩为单块最大容量存储器的测试时间。电熔丝测试控制采用状态机和编程加速逻辑,简化了测试接口,并消除了冗余的编程时间(0%～100%)。本文的各种可测试性设计策略在实际产品中已经得到验证,可广泛应用于复杂的片上系统(SoC)的设计,研究结论具有一定的应用参考价值。A digital audio codec System on a Chip with USB 2.0 full speed interface is described,which integrates three SPRAM,one DPRAM,three ROM,two POR,three LDO,one PLL,one e-fuse-box,one ADC,one USB PHY and digital logic in UMC 0.13μm CMOS process.Every analog macro is tested by using JTAG and PCL（Pad Control Logic） to control the test process.Dummy flip-flops are inserted and high fault coverage of 98.06% is achieved which meets the system design requirement.Memories could be tested in parallel and debugged in series,and the overall memory test time is reduced to the test time of one memory which has the maximum size.The e-fuse test is controlled by using finite state machine which simplifies the test interface,and programming acceleration logic which optimizes the redundant programming time（ranging from 0% to 100%）.All the test strategies presented here are silicon proved and can be widely used in the flow of complicated SoC design.

关 键 词：测试控制 测试时间优化 存储器内建自测试 电熔丝 

分 类 号：TN492[电子电信—微电子学与固体电子学]