State-of-the-art flash memory devices and post-flash emerging memories  

作　　者：LU ChihYuan LUE HangTing 

机构地区：[1]Macronix International Co., Ltd., 16 Li-Hsin Road, Hsinchu Science Park, Hsinchu

出　　处：《Science China(Information Sciences)》2011年第5期1039-1060,共22页中国科学（信息科学）（英文版）

摘　　要：Although conventional Floating gate （FG） flash memory has recently gone into the 2X nm node, the technology challenges are formidable below 20 nm. Charge-trapping （CT） devices are promising to scale beyond 20 nm but below 10 nm both CT and FG devices hold too few electrons for robust MLC （multi-level cell, or more than one bit storage per cell） storage. However, due to the simpler structure and its more robust storage （not sensitive to tunnel oxide defects since charges are stored in deep trap levels）, CT is much more desirable than FG in 3D stackable Flash memory. Optimistically, 3D CT Flash memory may allow the density increase to continue for at least another decade beyond the 1Xnm node. In this paper, we review the current status of FG devices, their scaling challenges, and the operation principles of CT devices and several variations such as MANOS and BF-SONOS. We will then discuss various 3D memory architectures, technology challenges and address the poly-silicon thin film transistor （TFT） issues. Devices that do not rely on charge storage are naturally not limited by the number of electrons, thus promise further scaling below 10 nm. Several of the most promising post-flash era devices, their operation principle and critical issues are reviewed. （One of them, phase change memory, will be covered in a separate article thus not included here.） Their potential applications and challenges for 3D stacking are critically examined.Although conventional Floating gate （FG） flash memory has recently gone into the 2X nm node, the technology challenges are formidable below 20 nm. Charge-trapping （CT） devices are promising to scale beyond 20 nm but below 10 nm both CT and FG devices hold too few electrons for robust MLC （multi-level cell, or more than one bit storage per cell） storage. However, due to the simpler structure and its more robust storage （not sensitive to tunnel oxide defects since charges are stored in deep trap levels）, CT is much more desirable than FG in 3D stackable Flash memory. Optimistically, 3D CT Flash memory may allow the density increase to continue for at least another decade beyond the 1Xnm node. In this paper, we review the current status of FG devices, their scaling challenges, and the operation principles of CT devices and several variations such as MANOS and BF-SONOS. We will then discuss various 3D memory architectures, technology challenges and address the poly-silicon thin film transistor （TFT） issues. Devices that do not rely on charge storage are naturally not limited by the number of electrons, thus promise further scaling below 10 nm. Several of the most promising post-flash era devices, their operation principle and critical issues are reviewed. （One of them, phase change memory, will be covered in a separate article thus not included here.） Their potential applications and challenges for 3D stacking are critically examined.

关 键 词：non-volatile memory charge-trapping （CT） device NOR Flash NAND Flash BE-SONOS 3DNAND VG NAND FERAM MRAM RERAM 

分 类 号：TP333[自动化与计算机技术—计算机系统结构] TP333.2[自动化与计算机技术—计算机科学与技术]