基于OpenRISC1200的H.264视频解码器片上系统设计  

Design of H.264 Video Decoder SoC Based on OpenRISC1200

作　　者：杨媛[1] 冯谋朝[1] 高勇[1] 刘宏泰 

机构地区：[1]西安理工大学电子工程系,西安710048 [2]中铁电气化局集团第三工程有限公司,郑州450000

出　　处：《固体电子学研究与进展》2011年第2期202-207,共6页Research & Progress of SSE

基　　金：陕西省自然科学基金资助项目(2009JQ8014);陕西省重点学科建设资助项目(10700-080903)

摘　　要：新一代的压缩标准H.264以其高压缩率与高图像质量而备受青睐,将H.264集成于SoC(片上系统Sys-tem on chip)已成为必然的发展趋势。基于开源免费的32位OpenRISC1200 CPU,设计了H.264解码器SoC系统,系统以OpenRISC1200为核心控制模块,其他所有外围模块包括H.264解码器模块、JTAG模块、UART模块、DMA模块、SDRAM、FLASH模块等均通过Wishbone片上总线与CPU通信。在软硬件的协同工作下,系统完成H.264视频图像的读取、解码和格式转换,最后通过VGA接口在CRT显示器上进行视频图像的显示。所设计的系统在Altera公司的FPGA EP2C70F672上进行了软硬件的协同验证,结果表明系统可以达到30 f/s的QCIF格式视频图像实时解码要求。For its high compression ratio and high image quality,the next-generation compression standard H.264 is much favorite,and integrating H.264 into SoC （System on chip） has become an inevitable trend.Based on open source free 32 bit OpenRISC1200 CPU,a H.264 decoder SoC system is designed.In the system OpenRISC1200 is acted as the core control module,all other peripheral modules,including H.264 decoder modules,JTAG module,UART modules,DMA module,SDRAM,FLASH module communicate with CPU through the on-chip Wishbone bus.In the hardware and software co-design,the reading,decoding and format conversion of H.264 video images are carried out,and the video images are displayed on CRT with VGA interface finally.The hardware and software co-verification of the system is realized in Altera＇s FPGA EP2C70F672 on,and the experiment results show that the system can achieve 30 f/s QCIF format video image real-time decoding requirement.

关 键 词：片上系统 解码器 H.264标准 

分 类 号：TN919.8[电子电信—通信与信息系统] TN432[电子电信—信息与通信工程]