超深亚微米数字电路的低功耗设计  

Low Power Design for Ultra-Deep-Submicron Digital Circuit

作　　者：李诗勤 

机构地区：[1]福州瑞芯微电子有限公司,福建福州350003

出　　处：《中国集成电路》2011年第5期25-30,52,共7页China lntegrated Circuit

摘　　要：随着集成电路逻辑复杂度日益提高,而工艺尺寸进入了超深亚微米数量级,低功耗设计已经成为整个SOC设计中关键的问题之一。电源电压是影响功耗的最重要因素,而阈值电压、体偏压和时钟频率也对功耗有影响。目前,对于数字电路,已经研发出一些有效地进行功耗管理,降低功耗的技术,并已应用于具体项目中。本文首先综述性地介绍几种低功耗设计方法,包括:多阈值电压CMOS技术;多电源电压;门控时钟;动态电压频率调制;动态体偏压调制;加入电源门控、以及状态可保持的电源门控技术,并逐一讨论了它们对降低功耗的具体作用。最后,针对最新的基于通用功耗格式的状态保持电源门控技术,本文概述其实现步骤。High complexity of applications and ultra-deep-submicron technologies make low-power become one of the most important metrics for the digital circuit in embedded SOC designs.Among all the influencing factors,power supply is the strongest handle.Meanwhile,threshold,body bias,and clock frequency have effects as well.To reduce power consumption,many tactics are developed and applied in the practical projects.In this paper,we present an overview of some key design measures for power saving that leverage voltage,threshold,clock frequency and body bias.These low-power approaches include:Multi-Threshold CMOS(MTCMOS),Multiple-Supply-Voltage(MSV),Clock Gating,Dynamic Voltage Frequency Scaling(DVFS),Active Body Bias(ABB),then Power Gating(PG) and State Retention Power Gating(SRPG).Characteristics of power states in all above techniques are discussed.Then implementation steps for Common-Power-Format based SRPG are provided.

关 键 词：超深亚微米 动态功耗 静态功耗 多阈值电压CMOS 多电源电压 动态电压频率调制 状态可保持的电源门控 通用功耗格式 

分 类 号：TN432[电子电信—微电子学与固体电子学]