一种基于FPGA的高速误码测试仪的设计  

FPGA-based design of high-speed bit error rate tester

作　　者：王骐[1] 王青萍[1] 

机构地区：[1]湖北第二师范学院物理与电子信息学院,湖北武汉430205

出　　处：《电子设计工程》2011年第9期129-133,共5页Electronic Design Engineering

摘　　要：误码测试仪是检测通信系统可靠性的重要设备。传统的误码测试仪基于CPLD和CPU协同工作,不仅结构复杂,价格昂贵,而且不方便携带。基于FPGA的高速误码测试仪,采用FPGA来完成控制和测试模块的一体化设计,提高了系统功能扩展性和系统的集成度,使得各个功能模块在不改动硬件电路的情况下可以相应变化。在发送端发送m序列作为测试数据,其测试速率最高可达到155 Mb/s。由于将物理层上的各协议层的功能集中到FPGA内部实现,减少了硬件和软件的设计复杂度,并且缩短了系统的开发的周期,具有可升级的特点。BBERT （Bit Error Rate Tester）is used in detecting for reliability of a communication system. The traditional design of BERT is based on CPLD and CPU＇s cooperative work. This traditional design has many disadvantages,such as complicate, cost much and inconvenient to taken..The project brings forward a configuration using the FPGA as the core chip. Using FPGA to complete the BERT＇s Control and test module design, it improves the system scalability and integration. Various functional modules can be altered accordingly without changing the hardware circuit. In the BERT Working Process,the transmitter sends M code as the test code. Its data rate is up to 155Mbps. It realizes the function of each protocol layer in physics layer, so it can reduce the hardware and software design complexity, and shorten the system development cycle, can be upgraded.

关 键 词：高速误码测试仪 现场可编程门阵列 VERILOG硬件描述语言 模块图元 仿真 M序列码 

分 类 号：TN609[电子电信—电路与系统]