基于适应度评价扩展自适应遗传算法的门级电路进化设计  

Evolutionary Design of Gate-level Circuits Based on Fitness Evaluation Expansion Adaptive Genetic Algorithm

作　　者：柏磊[1] 顾陈[1] 严璐 朱晓华[1] 

机构地区：[1]南京理工大学电子工程与光电技术学院,江苏南京210094 [2]南京莱斯信息技术股份有限公司智能交通事业部,江苏南京210007

出　　处：《南京理工大学学报》2011年第2期240-244,共5页Journal of Nanjing University of Science and Technology

摘　　要：针对遗传算法适应度评价阶段指定输出单元容易丢失潜在解的问题,该文提出了一种基于适应度评价扩展的电路进化设计方法。该方法将每个逻辑单元的输出都视为一个潜在的解处理,得到一个最优适应度评价值,避免了潜在解的丢失,有效地提高了自适应遗传算法的性能。通过多种电路的进化设计实验比较了该文方法与传统自适应遗传算法设计的性能,结果表明,该文方法具有收敛速度快、迭代次数少、获得最优解成功概率高的优点。To solve the problem of losing potential solution in specifying output cells at fitness evaluation stage of genetic algorithm,a new method based on fitness evaluation expansion adaptive genetic algorithm is proposed here.The method takes the output of every single cell in the evolved array as a potential solution,obtaining a best fitness evaluation value.The proposed method enhances the performance of adaptive genetic algorithm due to avoiding the loss of potential solution.Compared with the conventional algorithm in evolutionary design of circuits,the proposed method has advantages of faster convergence,less iteration and higher probability of obtaining desired solution.

关 键 词：电路进化设计 适应度评价扩展 门级电路 自适应遗传算法 可进化硬件 

分 类 号：TP18[自动化与计算机技术—控制理论与控制工程] TN702[自动化与计算机技术—控制科学与工程]