EDGE体系结构块预测器实现及改进  

Implementation and Improvement of Block Predictor in EDGE Architecture

作　　者：金鹰翰[1] 苟鹏飞[1] 王进祥[1] 

机构地区：[1]哈尔滨工业大学微电子中心,哈尔滨150001

出　　处：《微处理机》2011年第1期11-14,17,共5页Microprocessors

摘　　要：近十年来显式通信指令集的体系结构(EDGE)成为处理器体系结构研究的重要方向,TIRPS、TFlex和Wavescalar等都是其具体实现。分支预测器是高性能处理器的重要结构,其性能严重影响处理器整体性能。首先分析了EDGE体系结构控制流预测的特点,并对TRIPS原型芯片块预测器进行建模。通过运行SPEC 2K分析该块预测器造成误预测的主要原因,并针对其采用感知器进行了改进,提高了预测器性能,对EDGE体系结构块预测器设计有借鉴价值。In the last decade,EDGE architecture becomes one of the most important directions in CPU architecture research.TRIPS,TFLex,and Wavescalar are all its instantiations.Branch predictor,whose performance affects the overall performance of CPU,is an important structures in high-performance processor.This paper analyzes the characterstic of control speculation in EDGE architecture and models block predictor in TRIPS prototype chip.By running SPEC 2K,this paper finds out the main resources of mispredictions,and improves the predictor with perceptron predictor.

关 键 词：块预测器 显式通信指令集 感知器 

分 类 号：TP338.8[自动化与计算机技术—计算机系统结构]