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作 者:WANG Hai ZHANG Min LIU Jie
机构地区:[1]Department of Measurement and Control, Xidian University, Xi' an 710071, China
出 处:《Chinese Science Bulletin》2011年第12期1285-1290,共6页
基 金:supported by the National Natural Science Foundation of China (10703004);the Fundamental Research Funds for the Central Universities (JY10000904004)
摘 要:This study proposes a high-resolution short time interval measurement system based on the Vernier delay line (VDL) method. It should be noted that the programmable delay elements (PDEs) in the Xilinx field programmable gate arrays (FPGAs) provide a novel realization of delay lines. The delay lines can provide an accurate delay difference of 50 ps, which is process, voltage and temperature (PVT) invariant. An excellent consistency for the delay lines can be achieved by adjusting the timing and layout to minimize the measurement errors. The resolution achieved was 58 ps. Experimental results indicate a measurement standard deviation of 36 ps, a differential nonlinearity (DNL) of 36 ps and integral nonlinearity (INL) of 14 ps. The system features high accuracy, easy implementation and low cost.This study proposes a high-resolution short time interval measurement system based on the Vernier delay line (VDL) method. It should be noted that the programmable delay elements (PDEs) in the Xilinx field programmable gate arrays (FPGAs) provide a novel realization of delay lines. The delay lines can provide an accurate delay difference of 50 ps, which is process, voltage and temperature (PVT) invariant. An excellent consistency for the delay lines can be achieved by adjusting the timing and layout to minimize the measurement errors. The resolution achieved was 58 ps. Experimental results indicate a measurement standard deviation of 36 ps, a differential nonlinearity (DNL) of 36 ps and integral nonlinearity (INL) of 14 ps. The system features high accuracy, easy implementation and low cost.
关 键 词:FPGA芯片 测量系统 时间间隔 高分辨率 现场可编程门阵列 XILINX 延迟线 积分非线性
分 类 号:TM935.15[电气工程—电力电子与电力传动]
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