AHB总线在密码SoC中的设计与应用  

Design and Application of AHB Bus in Cryptographic SoC

作　　者：王瑞蛟[1] 张鲁国[1] 张文政[2] 

机构地区：[1]信息工程大学电子技术学院,河南郑州450004 [2]保密通信重点实验室,四川成都610041

出　　处：《信息安全与通信保密》2011年第6期75-77,共3页Information Security and Communications Privacy

摘　　要：为了提高密码SoC的接口的规范性能和系统的整体性能,提出了一个基于AMBA总线规范高性能总线AHB的多密码算法IP核的集成方案。首先对AHB高性能总线进行了FPGA实现,并在此基础上实现了多个密码算法IP核与AHB总线的挂接,完成了基于AHB总线的片上系统集成。最后对AHB总线和密码算法集成进行了仿真和FPGA测试,并验证了实现的正确性。In order to improve the interface specification and the overall performance of cryptographic SoC,an integrated scheme of cryptography IP cores based on AHB bus is proposed. According to AMBA specification,AHB bus is implemented on FPGA. Then a system integrating multi-cryptographic IP cores on AHB bus is realized. Finally,the AHB bus is simulated with ModelSim,and the integrated system is tested and verified on FPGA.

关 键 词：AHB总线 IP核 片上系统集成 密码算法 

分 类 号：TN47[电子电信—微电子学与固体电子学]