2 GHz CMOS高速多模分频器的设计  

Design of 2 GHz CMOS high sppedmulti-modulus frequency dividers

作　　者：张为[1] 张旭[1] 刘洋[1] 

机构地区：[1]天津大学电子信息工程学院,天津300072

出　　处：《华中科技大学学报（自然科学版）》2011年第5期113-117,共5页Journal of Huazhong University of Science and Technology(Natural Science Edition)

基　　金：天津市应用基础及前沿技术研究计划重点资助项目(10ZCKFGX03600)

摘　　要：为兼顾高速工作与多模分频应用,采用高速预分频电路与多模分频电路相结合的方式,提出了一种改进型的电流模型逻辑(CML)分频器.其中高速预分频电路由CML结构构成,多模分频电路利用相位切换结构和编程计数器共同实现.该分频器可在实现满摆幅输出的同时在更低的电源电压工作,从而消除了使用电平移位电路完成CML到互补金属氧化物半导体(CMOS)逻辑转换的需求.基于Chartered 0.18μm RFCMOS工艺流片完成了测试,分频器工作频率可达2GHz,工作电压为3.3V时功耗约为8.8mW.该高速多模分频器已成功应用于PLL型频率合成器.To consider high speed work and multi-modulus division applications, a prescaler based on current mode logic （CML） structure was combined with the multi-modulus frequency dividers, including a phase-switching circuit and programmable counters. In order to decrease the power consumption and the circuit complexity, an improved CML divider was designed, which has the full output swing and can operate under lower power supply. The level shifter for linking traditional CML to CMOS （complementry metal oxide semiconductor） logic was eliminated. The high speed multi-modulus frequency divider was fabricated under Chartered 0. 18 μm RF CMOS technology. The measurement results indicate that the divider can work at the frequency of 2 GHz and the power consumption is about 8.8 mW under 3.3 V supply. It had been used in a PLL frequency synthesizer successfully.

关 键 词：电流模式逻辑(CML) 相位切换 编程计数 频率合成器 满摆幅 

分 类 号：TN495[电子电信—微电子学与固体电子学]