A fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system in 0.13μm CMOS  

作　　者：楼文峰 耿志卿 冯鹏 吴南健 

机构地区：[1]Institute of Semiconductors,Chinese Academy of Sciences [2]Institute of Microelectronics,Tsinghua University

出　　处：《Journal of Semiconductors》2011年第6期84-90,共7页半导体学报（英文版）

基　　金：Project supported by the Chinese National High-Tech Research and Development Program(Nos2009ZX03007-001,2009AA011606);the National Natural Science Foundation of China(No60976023)

摘　　要：This paper proposes a sigma-delta fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system.With reasonable frequency planning,the system can be used in multi-standard wireless communication applications（GSM,WCDMA,GPRS,TD-SCDMA,WLAN（802.11a/b/g））.The implementation is achieved by a 0.13μm RF CMOS process.The measured results demonstrate that three quadrature VCOs（QVCO） continuously cover the frequency from 3.1 to 6.1 GHz（65.2%）,and through the successive divide-by-2 prescalers to achieve the frequency from 0.75 to 6.1 GHz continuously.The chip was fully integrated with the exception of an off-chip filter.The entire chip area is only 3.78 mm^2,and the system consumes a 21.7 mA@1.2 V supply without output buffers.The lock-in time of the PLL frequency synthesizer is less than 4μs over the entire frequency range with a direct frequency presetting technique and the auxiliary non-volatile memory（NVM）can store the digital configuration signal of the system,including presetting signals to avoid the calibration process case by case.This paper proposes a sigma-delta fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system.With reasonable frequency planning,the system can be used in multi-standard wireless communication applications（GSM,WCDMA,GPRS,TD-SCDMA,WLAN（802.11a/b/g））.The implementation is achieved by a 0.13μm RF CMOS process.The measured results demonstrate that three quadrature VCOs（QVCO） continuously cover the frequency from 3.1 to 6.1 GHz（65.2%）,and through the successive divide-by-2 prescalers to achieve the frequency from 0.75 to 6.1 GHz continuously.The chip was fully integrated with the exception of an off-chip filter.The entire chip area is only 3.78 mm^2,and the system consumes a 21.7 mA@1.2 V supply without output buffers.The lock-in time of the PLL frequency synthesizer is less than 4μs over the entire frequency range with a direct frequency presetting technique and the auxiliary non-volatile memory（NVM）can store the digital configuration signal of the system,including presetting signals to avoid the calibration process case by case.

关 键 词：fractional-N synthesizer Δ∑modulator MULTI-STANDARD quadrature VCO DIVIDE-BY-2 NVM 

分 类 号：TN74[电子电信—电路与系统] TN929.11