DIVIDE-BY-2

作品数：6被引量：8H指数：2
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相关领域：电子电信更多>>
相关作者：池保勇石秉学更多>>
相关机构：清华大学更多>>
相关期刊：《Journal of Electronic Science and Technology》《Journal of Semiconductors》更多>>
相关基金：国家自然科学基金国家重点基础研究发展计划更多>>
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Large-Capacity and High-Speed Instruction Cache Based on Divide-by-2 Memory Banks被引量：1
《Journal of Electronic Science and Technology》2021年第4期335-349,共15页Qing-Qing Li Zhi-Guo Yu Yi Sun Jing-He Wei Xiao-Feng Gu 
the Postgraduate Research Innovation Program of Jiangsu Province under Grant No.KYCX20_1936;the Fundamental Research Funds for the Central Universities under Grant No.JUSRP51510;the Key Research and Development Program of Jiangsu under Grant No.BE2019003-2.
An increase in the cache capacity is usually accompanied by a decrease in access speed.To balance the capacity and performance of caches,this paper proposes an instruction cache(ICache)architecture based on divide-by-...
关键词：Cache capacity expansion divide-by-2 frequency instruction cache(ICache) inversed clock. 
A fractional-N frequency synthesizer for wireless sensor network nodes被引量：3
《Journal of Semiconductors》2014年第12期68-73,共6页马骁 杜占坤 刘畅 刘珂 阎跃鹏 叶甜春 
supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China(Nos.2010ZX03006-003-02,2012ZX03004-006)
This paper presents a fractional-N frequency synthesizer for wireless sensor network（WSN） nodes. The proposed frequency synthesizer adopts a phase locked loop（PLL） based structure, which employs an LC voltagecontr...
关键词：WSN frequency synthesizer KVCO variation DIVIDE-BY-2 
A 7-27 GHz DSCL divide-by-2 frequency divider
《Journal of Semiconductors》2012年第10期92-96,共5页郭婷 李智群 李芹 王志功 
supported by the National Basic Research Program of China(No.2010CB327404);the National Natural Science Foundation of China(No.60901012)
This paper presents the design and analysis of a high speed broadband divide-by-2 frequency divider. The proposed divider is a dynamic source-coupled logic（DSCL） structure formed with two dynamic-loading master-slav...
关键词：BROADBAND frequency divider dynamic source-coupled logic dynamic-loading input-sensitivity CMOS 
Low power fast settling multi-standard current reusing CMOS fractional-N frequency synthesizer被引量：2
《Journal of Semiconductors》2012年第4期95-104,共10页楼文峰 冯鹏 王海永 吴南健 
Project supported by the National Natural Science Foundation of China(No.60976023);the National Science and Technology Major Project of China(Nos.2009ZX03007-001,2012ZX03004007-002)
A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard f...
关键词：phase-locked loop current reusing forward-body bias DIVIDE-BY-2 MULTI-STANDARD fast settling 
A fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system in 0.13μm CMOS被引量：1
《Journal of Semiconductors》2011年第6期84-90,共7页楼文峰 耿志卿 冯鹏 吴南健 
Project supported by the Chinese National High-Tech Research and Development Program(Nos2009ZX03007-001,2009AA011606);the National Natural Science Foundation of China(No60976023)
This paper proposes a sigma-delta fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system.With reasonable frequency planning,the system can be used in multi-standard wireless communicatio...
关键词：fractional-N synthesizer Δ∑modulator MULTI-STANDARD quadrature VCO DIVIDE-BY-2 NVM 
Integrated Low-Power CMOS VCO and Its Divide-by-2 Dividers被引量：1
《Journal of Semiconductors》2002年第12期1262-1266,共5页池保勇 石秉学 
An integrated low power CMOS VCO and its divide by 2 dividers for WLAN transceivers are presented.The VCO is based on on chip symmetrical spiral inductor and differential diode and the divide by 2 dividers are b...
关键词：VCO WLAN transceivers divide  by  2 divider 
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