A fractional-N frequency synthesizer for wireless sensor network nodes  

作　　者：马骁 杜占坤 刘畅 刘珂 阎跃鹏 叶甜春 

机构地区：[1]Institute of Microelectronics,Chinese Academy of Sciences

出　　处：《Journal of Semiconductors》2014年第12期68-73,共6页半导体学报（英文版）

基　　金：supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China(Nos.2010ZX03006-003-02,2012ZX03004-006)

摘　　要：This paper presents a fractional-N frequency synthesizer for wireless sensor network（WSN） nodes. The proposed frequency synthesizer adopts a phase locked loop（PLL） based structure, which employs an LC voltagecontrolled oscillator（VCO） with small VCO gain（KVCO） and frequency step（fstep） variations, a charge pump（CP）with current changing in proportion with the division ratio and a 20-bit △∑ modulator, etc. To realize constant KVCO and fstep, a novel capacitor sub-bands grouping method is proposed. The VCO sub-groups＇ sizes are arranged according to the maximal allowed KVCOvariation of the system. Besides, a current mode logic divide-by-2 circuit with inside-loop buffers ensures the synthesizer generates I/Q quadrature signals robustly. This synthesizer is implemented in a 0.13μm CMOS process. Measurement results show that the frequency synthesizer has a frequency span from 2.07 to 3.11 GHz and the typical phase noise is 86：34 dBc/Hz at 100 k Hz offset and 114：17 dBc/Hz at 1 MHz offset with a loop bandwidth of about 200 k Hz, which meet the WSN nodes＇ requirements.This paper presents a fractional-N frequency synthesizer for wireless sensor network（WSN） nodes. The proposed frequency synthesizer adopts a phase locked loop（PLL） based structure, which employs an LC voltagecontrolled oscillator（VCO） with small VCO gain（KVCO） and frequency step（fstep） variations, a charge pump（CP）with current changing in proportion with the division ratio and a 20-bit △∑ modulator, etc. To realize constant KVCO and fstep, a novel capacitor sub-bands grouping method is proposed. The VCO sub-groups＇ sizes are arranged according to the maximal allowed KVCOvariation of the system. Besides, a current mode logic divide-by-2 circuit with inside-loop buffers ensures the synthesizer generates I/Q quadrature signals robustly. This synthesizer is implemented in a 0.13μm CMOS process. Measurement results show that the frequency synthesizer has a frequency span from 2.07 to 3.11 GHz and the typical phase noise is 86：34 dBc/Hz at 100 k Hz offset and 114：17 dBc/Hz at 1 MHz offset with a loop bandwidth of about 200 k Hz, which meet the WSN nodes＇ requirements.

关 键 词：WSN frequency synthesizer KVCO variation DIVIDE-BY-2 

分 类 号：TN74[电子电信—电路与系统] TP212[自动化与计算机技术—检测技术与自动化装置]