Low power fast settling multi-standard current reusing CMOS fractional-N frequency synthesizer  

作　　者：楼文峰 冯鹏 王海永 吴南健 

机构地区：[1]State Key Laboratory for Superlattices and Microstructures,Institute of Semiconductors,Chinese Academy of Sciences,Beijing 100083,China

出　　处：《Journal of Semiconductors》2012年第4期95-104,共10页半导体学报（英文版）

基　　金：Project supported by the National Natural Science Foundation of China(No.60976023);the National Science and Technology Major Project of China(Nos.2009ZX03007-001,2012ZX03004007-002)

摘　　要：A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer. An auxiliary non-volatile memory （NVM） is embedded to avoid the repetitive calibration process and to save power in practical application. This PLL is implemented in a 0.18 #m technology. The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5 #s over the entire frequency range. The LC-VCO with the stacked divide-by-2 has a good figure of merit of-193.5 dBc/Hz. The measured phase noise of frequency synthesizer is about -115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than -52 dBc. The whole frequency synthesizer consumes only 4.35 mA @ 1.8 V.A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer. An auxiliary non-volatile memory （NVM） is embedded to avoid the repetitive calibration process and to save power in practical application. This PLL is implemented in a 0.18 #m technology. The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5 #s over the entire frequency range. The LC-VCO with the stacked divide-by-2 has a good figure of merit of-193.5 dBc/Hz. The measured phase noise of frequency synthesizer is about -115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than -52 dBc. The whole frequency synthesizer consumes only 4.35 mA @ 1.8 V.

关 键 词：phase-locked loop current reusing forward-body bias DIVIDE-BY-2 MULTI-STANDARD fast settling 

分 类 号：TN74[电子电信—电路与系统] TN432