嵌入式微处理器分支预测的设计与实现  

Design and realization of branch prediction for embedded microprocessor

作　　者：陈海民[1] 李峥[1] 王瑞蛟[1] 

机构地区：[1]信息工程大学电子技术学院,郑州450004

出　　处：《计算机应用》2011年第7期2004-2007,共4页journal of Computer Applications

基　　金：国家自然科学基金资助项目(61072047);郑州市创新型科技人才队伍建设工程项目(096SYJH21099);现代通信国家重点实验室基金资助项目(9140C1106021006)

摘　　要：针对五级流水线嵌入式微处理器的特定应用环境,对分支预测技术进行了深入研究,提出了一种新的分支预测方案。该方案兼容带缓存设计,通过扩展指令总线,在取指段提前对分支指令跳转方向和目标地址进行预测,保存可能执行而未执行的指令和地址指针以备分支预测失效时得以恢复,减少了预测失效的代价,同时保证了指令流的正确执行。研究表明,该方案硬件开销小,预测效率高,预测失效代价低。Concerning the specific application environment of embedded microprocessor,the branch prediction technology was researched in this paper,and a new scheme of branch prediction was proposed.Compatible with cache design,jump direction and destination address of branch prediction happened on extended instruction bus.The unexecuted instruction and address pointer were saved for possible recovery after misprediction,which reduced misprediction penalty,simultaneously guaranteed the instruction flow to execute correctly.The study shows this scheme is of little hardware spending,high prediction efficiency and low misprediction penalty.

关 键 词：嵌入式微处理器 流水线 ARM指令集 分支预测 失效代价 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]