注入势垒单相埋沟高速CCD延迟线设计  

Design of Implanted-Barrier Single-Phase Buried-Channel High-Speed CCD Delay Line

作　　者：杨亚生[1] 

机构地区：[1]重庆光电技术研究所,重庆400060

出　　处：《微电子学》2011年第3期420-423,432,共5页Microelectronics

摘　　要：采用注入势垒单相埋沟结构和两层多晶硅一层铝工艺技术,研制出512位高速CCD延迟线,获得了大于10 MHz的工作频率和大于50 dB的动态范围。器件电极设计为准1相两层多晶硅交迭栅结构,信道设计为埋沟结构。输入结构采用双输入栅表面势平衡注入技术,输出结构采用浮置扩散源跟随放大器技术。提出了改善转移效率、暗电流、时钟频率和动态范围的有效方法。测试结果表明,器件性能参数达到设计要求。A 512-bit high-speed CCD delay line with operating frequency greater than 10 MHz and dynamic range over 50 dB was fabricated using implanted-barrier single-phase buried-channel structure and 2-polysilicon 1-aluminum processing technology.Electrodes of quasi-single-phase 2-polysilicon-layer overlapping-gate structure were designed for the device,and buried structure was used for channel.The input structure was achieved by double-input gate surface potential balanced injection,and floating diffusion source follower amplifier was employed for output structure.Methods to effectively improve transfer efficiency,clock frequency,dynamic range and reduce dark current were proposed.Test results showed that the device performance reached the design target.

关 键 词：势垒 埋沟CCD 延迟线 

分 类 号：TN43[电子电信—微电子学与固体电子学]