高压抗噪声干扰MOS栅驱动电路的设计  

Design of MOS gate drive circuit with high voltage and noise immunity

作　　者：初秀琴[1,2] 王雪燕[1,3] 王松林[1,3] 赵永瑞[1,2] 

机构地区：[1]西安电子科技大学电路CAD研究所,陕西西安710071 [2]西安电子科技大学超高速电路设计与电磁兼容教育部重点实验室,陕西西安710071 [3]西安电子科技大学机电工程学院,陕西西安710071

出　　处：《华中科技大学学报（自然科学版）》2011年第6期50-53,共4页Journal of Huazhong University of Science and Technology(Natural Science Edition)

基　　金：国家自然科学基金资助项目(60876023)

摘　　要：设计了一种高压抗噪声干扰MOS栅驱动电路,能有效抑制开关转换过程中产生的dv/dt噪声,消除高压电路工作过程中可能出现的误触发,提高系统的稳定性和可靠性.采用共模反馈从而使电路结构简单,同时采用窄脉冲触发式控制降低了功耗.本电路可以集成在高压集成电路(HVIC)中.采用某公司高压600V0.5μm BCD工艺模型,通过Cadence仿真验证表明:本电路可有效滤除dv/dt噪声,被消除的dv/dt噪声最高可以达到60V/ns,同时被消除的失调噪声可以达到20%,保证了高压栅驱动电路稳定、可靠地工作.A MOS gate drive circuit with noise immunity of high voltage was designed, by which the high dv/dr noise occurring during the process of switch conversion could be effectively inhibited, the wrong trigger could be eliminated during the working of high-voltage circuit and the stability and reliability of the system would be improved. With its simple structure by using common feedback and the lower power consumption by using narrow-pulse triggering control, the circuit is integrated in the high voltage integrated circuit （HVIC）. Using the high voltage of 600 V and 0.5 μm BCD （Bipolar- CMOS-DMOS） process model, the simulation result by Cadence indicates that the circuit can effectively filter out the dv/dt noise, which is eliminated by up to the rate of 60 V/ns and the diamatched can be to 20%, ensurimg the work of the high-voltage MOS gate drive circuit stable and reliable.

关 键 词：高压集成电路 MOS栅驱动电路 开关转换 共模反馈 窄脉冲触发 

分 类 号：TN432[电子电信—微电子学与固体电子学]