基于CPLD虚拟逻辑分析仪设计  

Design of Virtual Logic Analyzer Based on CPLD

作　　者：蒋炜华[1] 周晓娟[1] 李宁 

机构地区：[1]河南机电高等专科学校电气工程系,河南新乡453002 [2]洛阳供电局电力设计院,河南洛阳417000

出　　处：《新乡学院学报》2011年第3期246-248,259,共4页Journal of Xinxiang University

摘　　要：逻辑分析仪用于涉及大量信号或复杂触发器要求的数字测量,以往的独立式逻辑分析仪不仅结构复杂,而且价格昂贵。设计了一种基于CPLD的虚拟逻辑分析仪,分析了虚拟逻辑分析仪的硬件电路和软件。以CPLD为主要功能实现平台,以单片机作为与计算机和CPLD之间的通信纽带,以可视化的形式在计算机上显示采集到的数据。采用VHDL语言进行各个功能模块的编程,最后,对程序进行编译和功能仿真,给出仿真结果,验证系统设计的正确性。仿真结果证明该虚拟逻辑分析仪不仅结构简单、成本较低,而且具有通道数量多、捕获速度快、性能稳定等特点。Logic analyzer is used for testing digital information in the system refers to mass signals or complicated trigger request,but the independent logic analyzer is not only expensive,but also its structure is complex.In this paper,a virtual logic analyzer based on CPLD is introduced,the design of circuit hardware and software are simplified.It based on functional platform of CPLD,Using the Single-chip computer as the communication link between CPLD and computer,collected data to visual displayed on the computer.The results,from programming modules,compiling and functional simulation,finally verified the correctness of system design.It has been proven in the practice that the structure of the virtual logic analyzer is simple and the cost is low,moreover it has multi channels and high sampling speed as well as its advantage of stability.

关 键 词：VHDL CPLD 虚拟 逻辑分析仪 仿真 单片机 

分 类 号：TN46[电子电信—微电子学与固体电子学]