ZnO纳米线阵列/p-Si异质结的合成及其整流特性  

Rectifying Behavior of Synthesized ZnO Nanowire Arrays/p-Si Heterojunction

作　　者：程萍[1] 田永涛[1] 王文闯[1] 徐玉睿[1] 何豪[1] 王新昌[1] 李新建[1] 

机构地区：[1]郑州大学物理工程学院材料物理教育部重点实验室,河南郑州450052

出　　处：《郑州大学学报（理学版）》2011年第3期87-90,共4页Journal of Zhengzhou University:Natural Science Edition

基　　金：国家自然科学基金资助项目;编号50602040;10574112;河南省重大科技攻关项目;编号082101510007;教育部科学技术重点研究项目;编号208048;河南省教育厅自然科学基金资助项目;编号2007140018

摘　　要：利用化学汽相沉积，在没有催化剂的p-si衬底上一步合成ZnO纳米线阵列，构成ZnO阵列／p-Si异质结．电流-电压性能测试显示该结构具有较好的整流特性，漏电流较小，4V时约为0．05mA．异质结理想因子偏高，1．86（0．5-2．25V）和5．92（在2．25-2．7V），主要原因可能ZnO纳米线阵列底与si之间存在较高的缺陷密度．提供了一种简单的合成ZnO阵列／p-Si异质结方法，不需要在si衬底上预先合成ZnO缓冲层和催化剂，同时结构具有较好整流性能，对ZnO器件的设计合成及应用有一定的参考价值．ZnO nanowire arrays were fabricated on p-Si substrate without catalyzes by CVD method to form ZnO nanowire arrays/p-Si heterojunctions. The ZnO arrays were irregular and vertical approximately. The I-V characteristics showed good rectifying behavior of the heterojunction with the small reverse saturation current. The value of the ideal factor of the heterojunction was 1.86 in the bias voltage range of 0.5 - 2.25 V and 5.92 in the voltage range of 2.25 - 2.7 V respectively. Many defects in the interface cased by the lattice mismatch between ZnO and p-Si may due to the high ideal factor. A simple method was approached to synthesize ZnO hetero-structures and our results were valuable for application and design of the ZnO nano-devices.

关 键 词：ZnO阵列 异质结 CVD法 整流 理想因子 

分 类 号：TB321[一般工业技术—材料科学与工程]