高稳定性无片外电容低压差线性稳压器的设计  

Design of the High-Stability Capacitor-Free Low Dropout Linear Voltage Regulator

作　　者：刘生有[1] 马骁[1] 杜占坤[1] 郭桂良[1] 阎跃鹏[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《半导体技术》2011年第7期538-541,共4页Semiconductor Technology

基　　金：国家高技术研究发展计划项目(2009AA12Z314)

摘　　要：设计了一款无片外电容低压差线性稳压器(LDO),与传统的LDO相比,此LDO消除了传统结构中所需的片外电容,可更好地应用于全集成低功耗的片上系统(SoC)中。针对无片外电容LDO没有外部等效零点补偿这一特点,采用一种折叠输入推挽输出误差放大器结构,结合密勒补偿以及一阶RC串联零点补偿两种方案,有效地改善了无片外电容LDO的稳定性。电路采用SMIC0.18μm CMOS工艺实现,面积为0.11 mm2,最大负载电容100 pF,输入电压为1.8 V时,输出电压为1.5 V,静态电流31.8μA,压差为160 mV。A capacitor-free low-dropout（LDO） linear voltage regulators was designed.Compared with the traditional one,the LDO eliminates the large off-chip capacitor,and can be better applied to fully integrated SoC with a merit of low power dissipation.Because this capacitor-free LDO has no external zero compensation,an error amplifier adopting folded-input and push-pull output structure is used in it.By this way,combined with Miller compensation and a zero compensation which is brought in by first-order equivalent series RC,the LDO stability problem caused by capacitor-free structure can be resolved.This design has been implemented in SMIC 0.18μm CMOS technology,occupies an area of 0.11 mm2,and can drive a maximum 100 pF load capacitance.With a 1.8 V input voltage,the output voltage,quiescent current and dropout voltage are 1.5 V,31.8 μA,and 160 mV,respectively.

关 键 词：无片外电容 低压差稳压器 密勒补偿 高稳定性 片上系统(SoC) 

分 类 号：TN432[电子电信—微电子学与固体电子学]