一种可重构的通用总线接口验证平台的研究及实现  

Research and Implementation of a Generic Reconfigurable Bus Interface-Based Verification Platform

作　　者：刘芳[1] 谢峥[1] 连志斌[1] 王新安[1] 

机构地区：[1]北京大学深圳研究生院集成微系统科学工程与应用重点实验室,广东深圳518055

出　　处：《电子器件》2011年第3期350-354,共5页Chinese Journal of Electron Devices

摘　　要：以UART总线接口为例介绍一种高性能验证平台。该验证平台基于SystemVerilog语言,以功能覆盖率为导向,通过带约束的随机方法产生测试激励,并具有自动检查运行结果及可重用性等特点。实践表明,与传统的验证平台相比,该平台在验证效率及功能覆盖率方面均有明显的优越性;与基于VMM搭建的验证平台相比,该平台也表现出了一定的灵活性、易操作性的特点。The bus interface UART was used as an example to introduce a high-performance verification platform.Based on System Verilog language,oriented towards the feedback of functional coverage,the platform generated test stimulus,and automatically checked the operating results.The platform has good features such as in reuse and efficiency.Practices showed that compared with the traditional verification platform,this platform has obvious advantages in terms of functional coverage and verifiable efficiency,and compared with VMM-based verification platform this platform shows its better features such as efficiency,flexibility,easy to learn and operating master.

关 键 词：UART SYSTEMVERILOG 带约束的随机方法 功能覆盖率 VMM 

分 类 号：TP216[自动化与计算机技术—检测技术与自动化装置]