LTE中卷积码的译码器设计与FPGA实现  

Design and FPGA Implementation of Decoder for Convolutional Code in LTE

作　　者：李冬冬[1] 

机构地区：[1]北京工业大学北京市嵌入式系统重点实验室,北京100124

出　　处：《现代电子技术》2011年第13期46-48,52,共4页Modern Electronics Technique

摘　　要：基于长期演进(LTE)的Tail-biting卷积码,介绍了维特比译码算法,它是一种最优的卷积码译码算法。由于Tail-biting卷积码的循环特性,采用固定延迟译码的方法,降低了译码复杂度。通过使用全并行的结构及简单的回溯存储方法,设计了一个具有高速和低复杂度的固定延迟译码器。在FPGA上实现并验证,验证结果表明译码器的性能满足了LTE系统的要求。Based on Tail-biting convolutional code of LTE, Viterbi Algorithm which is a optimal decoding algorithm of convolutional codes is introduced. The fixed-delay decoding scheme is adopted to reduce the decoding complexity according to the circular property of Tail-biting convolutional code. By using all parallel structure and simple trace back memory method, a fixed-delay decoder with higher speed and lower complexity is designed. The decoder was implemented and verified with FPGA. The results of verification show that the performance of the decoder meets the requirements of LTE syetem.

关 键 词：LTE Tail—biting卷积码 维特比译码算法 固定延迟译码 FPGA 

分 类 号：TN764[电子电信—电路与系统]