基于FPGA的ISA总线接口逻辑设计  

The Logical Design of ISA Bus Interface Based on FPGA

作　　者：沈晓红[1] 鲁延峰[1] 李凯 

机构地区：[1]北京工商大学机械工程学院,北京100048

出　　处：《微计算机信息》2011年第7期110-111,共2页Control & Automation

摘　　要：虽然各种新式总线相继出现,但ISA总线在工业领域应用相当普遍,本文提出用Verilog HDL语言写FPGA(可编程逻辑门阵列)逻辑来实现ISA总线的接口设计,可以大大减化硬件电路设计复杂的缺点,灵活简单。将设计的接口逻辑用于超声波探伤卡的ISA接口中得以验证。Although a variety of new bus after another, but the application of ISA bus is very common in the areas of Industry, this paper uses the Verilog HDL language to write FPGA （Field-Programmable Gate Array） logic to achieve the ISA bus interface design can be greatly simplified hardware design complexity the shortcomings of simple and flexible. The design of the interface logic for the ultrasonic testing card of the ISA interface to verify.

关 键 词：FPGA ISA总线 VERILOG HDL 

分 类 号：TP274.2[自动化与计算机技术—检测技术与自动化装置]