芯片尺寸封装焊点的可靠性分析与测试  

Reliability analysis and testing of chip scale package solder joint

作　　者：杨虹蓁[1] 曹白杨[1] 曹新宇[1] 

机构地区：[1]北华航天工业学院电子工程系,河北廊坊065000

出　　处：《电子元件与材料》2011年第8期63-66,共4页Electronic Components And Materials

基　　金：河北省高等学校科学技术研究指导项目资助(No.Z2010202)

摘　　要：利用ANSYS有限元分析软件,将芯片尺寸封装(CSP)组件简化为了二维模型,并模拟了CSP组件在热循环加载条件下的应力应变分布;通过模拟发现了组件的结构失效危险点,然后对危险点处的焊点热疲劳寿命进行了预测;最后进行了CSP焊点可靠性测试。结果表明,用薄芯片可提高焊点可靠性。当芯片厚度从0.625 mm减小到0.500 mm和0.350 mm时,焊点的可靠性分别提高了约0.75和1.5倍。Using ANSYS finite element analysis software,a simple two-dimensional model was built for chip scale package（CSP） components,and then the stress and strain distribution of CSP components under thermal cycling were simulated with this model.The dangerous point of CSP components structural failure was found through simulation,and the thermal fatigue life of solder joints at the dangerous point was then predicted.Finally,the reliability of CSP solder joints was tested.The results show that using thin chips can improve the reliability of solder joints.When chip thickness decreases from 0.625 mm to 0.500 mm and 0.350 mm,the reliability of solder joints increases by about 75% and 150%,respectively.

关 键 词：芯片尺寸封装 有限元分析 焊点 可靠性 

分 类 号：TN306[电子电信—物理电子学]