防火墙寄存器技术的FPGA低功耗布线算法研究  

Low power FPGA routing algorithm based on firewall register

作　　者：黄娟[1,2] 杨海钢[1] 谭宜涛[1,2] 崔秀海[1] 李威[1] 

机构地区：[1]中国科学院电子学研究所可编程芯片与系统研究室,北京100190 [2]中国科学院研究生院,北京100039

出　　处：《计算机应用研究》2011年第8期2954-2957,共4页Application Research of Computers

基　　金：国家重大科学研究计划资助项目(2011CB933202)

摘　　要：针对减少毛刺能够有效地降低电路功耗,提出了一种基于防火墙寄存器技术的FPGA低功耗布线算法。在布线过程中,一方面运用算法增加防火墙寄存器滤掉毛刺;另一方面通过修改代价函数,动态地调节输入信号的路径,使信号到达查找表输入端的时间基本趋于一致,从而有效地减少毛刺,降低电路的动态功耗。实验结果表明,在运算时间相同的情况下,与其他算法相比,该算法平均能消除约72%～81%的毛刺,降低约4%～8%的功耗,减少约23%～26%的关键路径延时,而只增加4%的触发器。This paper described a routing algorithm relaying on firewall register that limited the number of glitches in order to reduce dynamic power in FPGAs.The idea was to activate unused flip-flops to block the propagation of glitches,basing on firewall register,modified cost function and aligned the arrival time of signals to the inputs of the lookup tables in order to filter out glitches.During the same run time,experiment results demonstrate that the proposed method eliminates 72%~81% of the glitches,reduces overall FPGA power by 4%~8% and the critical-path delay by 23%~26%,while,compared with the other routing algorithms,the flip-flops only increases by 4% on average.Furthermore,the proposed method requires no additional hardware to reduce glitches.

关 键 词：FPGA 防火墙寄存器 低功耗布线 毛刺 查找表 

分 类 号：TP301[自动化与计算机技术—计算机系统结构]