占空比为50%的数控分频器设计及实现  

Design and Implementation of the Numerical Control Frequency Divider with 50%

作　　者：徐尚中[1] 牛玲[1] 

机构地区：[1]河南周口师范学院计算机科学系

出　　处：《现代计算机（中旬刊）》2011年第6期74-76,共3页Modern Computer

基　　金：河南省教育厅自然科学项目(No.2010B520035)

摘　　要：针对FPGA外部时钟信号过高的特点,在分析偶数分频和奇数分频的基础上,采用VHDL设计一种占空比为50%的数控分频器,并在QuartusⅡ环境下进行仿真实验。实验结果表明,设计方案是可行的,具有很强的实用价值。Aiming at the characteristic that FPGA external clock sign is too high,designs a numerical control frequency divider by using VHDL based on the analysis of even frequency division and odd frequency division.And simulates in Quartus II.The experimental result shows that the design of the frequency divider is feasible.

关 键 词：数控分频 VHDL FPGA 仿真 

分 类 号：TN912.26[电子电信—通信与信息系统]