采用同步分析的零延迟GRLS通信机制  

Synchronous Mechanisms Based Zero-Latency GRLS Communication Scheme

作　　者：王茹[1,2,3] 王焕东[1,2,3] 范宝峡[1,3] 杨梁[3] 

机构地区：[1]中国科学院计算技术研究所微处理器中心,北京100190 [2]中国科学院研究生院,北京100049 [3]北京龙芯中科技术服务中心有限公司,北京100190

出　　处：《计算机辅助设计与图形学学报》2011年第8期1455-1462,共8页Journal of Computer-Aided Design & Computer Graphics

基　　金：国家"九七三"重点基础研究发展计划项目(2005CB321600);国家"八六三"高技术研究发展计划(2009AA01Z125);国家自然科学基金(60803029;60801045)

摘　　要：全局异步局部同步(GALS)与频率调整相结合能够有效地降低动态功耗.针对频率切换以及跨时钟域传输开销会损害芯片性能的问题,提出一种基于计数器的分频方法.该方法根据计数结果生成分频后的时钟沿,并在此基础上建立了一个全局比例同步局部同步(GRLS)的通信机制.GRLS利用2个时钟的频率及相位关系实现了零延迟的跨时钟域传输,并引进同步电路分析方法来保证其正确性和健壮性;GRLS不会对原有的时钟设计做任何改变,频率切换可以在一个周期内完成,且面积功耗开销可以忽略不计.最后通过基于GRLS建立的存储系统证明了该机制的高效性.目前GRLS已经成功地应用于一款商业SoC.Globally asynchronous locally synchronous （GALS） combined with frequency scaling has become a popular and effective technique in chip power reduction. However, frequency switching penalty and crossing domain communication may be harmful to the performance of design. This paper introduces a counter based frequency scaling method, in which the new clock edges are generated according to the results of the counter. Based on this method a globally ratiochronous locally synchronous （GRLS） scheme is proposed. GRLS is targeting at communication between two clock domains whose frequencies are ratio-related. By use of the relationship on frequency and phase, synchronous mechanisms are employed to maintain the correctness and robustness of the scheme. ORLS achieves a zero-latency crossing-domain communication. Frequency switching can be finished in a cycle and the power and area penalties can be neglected. Experimental results of a memory system built with GRLS demonstrated its efficiency, and GRLS has been successfully applied in a commercial SoC.

关 键 词：全局异步局部同步 全局比例同步局部同步 频率比例 零延迟 同步机制 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]