基于折叠的DDC抽取器设计  

Design of DDC Extractor based on Folded Structure

作　　者：冉旋[1] 凌翔[1] 

机构地区：[1]电子科技大学,四川成都611731

出　　处：《通信技术》2011年第8期33-35,129,共4页Communications Technology

摘　　要：基于FPGA利用CIC和HB滤波器实现DDC抽取器是一种高效方法,但传统设计很少考虑资源优化问题。介绍了一种基于折叠技术的资源复用设计方法,通过对运算硬件资源复用的合理控制,可以减少硬件资源开销或减小硅片面积。由折叠方程分别推导出CIC和HB的折叠实现框图,用Verilog描述了设计,经MATLAB与Modelsim联合仿真后,最终在Xilinx公司的xc4vfx20 FPGA上应用于系统。同步时钟设计,在满足低延迟等性能要求下,具有耗费资源少、功耗低、稳定性高等优点。To realize the Digital-Down-Convertor extractor,the employment of Cascaded-Integrator-Comb filter and the Half-Band filter with FPGA is an efficient way.However,the traditional design method seldom considers the limited area resources.This paper proposes a new design method based on folding technique,and this method could implement a time-multiplexed structure,and thus could save the function unit resources or the silicon area.The CIC and HB folding diagrams are derived with folding equation,and then coded with Verilog.Through the co-simulation of modelsim and matlab this design is successfully applied on Xilinx＇s xc4vfx20 FPGA.Synchronous clock design,with satisfaction in low latency and other performance requirements,is of prominent advantages of less area resources,lower power consumption,and higher stability.

关 键 词：数字下变频 积分梳状滤波器 半带滤波器 折叠 VERILOG 

分 类 号：TN911.72[电子电信—通信与信息系统]