一种简易MCU的加法器设计方法  

A simplified method of the MCU adder design

作　　者：张恒[1] 江猛 

机构地区：[1]苏州经贸职业技术学院机电系,江苏苏州215009 [2]苏州华芯微电子有限公司,江苏苏州215011

出　　处：《信息与电子工程》2011年第4期507-509,514,共4页information and electronic engineering

摘　　要：算术逻辑部件(ALU)是整个微控制单元(MCU)运算的核心,相当于人类的大脑。ALU的运算性能直接影响整个MCU运行的效率。一般简易MCU的内核只需进行加、减、逻辑运算等,不涉及到乘除,针对此特点设计了一种简易的加法电路,并在FPGA下进行仿真验证,仿真结果达到了设计要求,该ALU部分能根据不同的使能信号实现加、减、逻辑与或非以及数据传输功能。Arithmetic Logic Unit（ALU） is the core of the Micro Control Unit（MCU） operation, equivalent to the human brain. The operation performance of ALU directly affects the efficiency of the entire running of MCU. General simple MCU cores need only add, subtract and logical operations, not involving multiplication and division. Aiming to this feature, a simple adder circuit is designed. The simulation verification under FPGA is performed, whose results meet the design requirements. The ALU part in the design can achieve the functions of addition, subtraction, logic and-or-not and data transferring according to the enabling signals.

关 键 词：微控制单元 算术逻辑部件 全加器 进位电路 

分 类 号：TP332.21[自动化与计算机技术—计算机系统结构]